RISC-V: The core pillar of China’s AI industry that is independent and controllable, and the ecological explosion period has arrived

1. RISC-V’s three core advantages in supporting AI independent controllability

1. The architecture is flexible and customizable, perfectly adapting to all AI scenarios.

• Modular instruction set: Basic instructions can be tailored as needed, and AI-specific vector (RVV)/tensor/matrix operation instructions can be expanded to avoid performance redundancy.
• Scenario customization：
  • Edge/Terminal: Cut out redundant units, enhance low power consumption, and adapt to smart cameras, sensors, robots, etc.
  • Cloud/server: Expand high-bandwidth interconnection, large memory, and multi-core collaboration to support large model inference and training
  • Special scenarios: Customize special acceleration instructions for NLP, computer vision, and autonomous driving, increasing computing power density by 50%~200%

2. Low power consumption and high energy efficiency, the optimal solution for edge AI

• Streamlined instructions: No redundant operation, the computing power per unit power consumption is 15%~30% higher than ARM and 40%~60% higher than x86
• Edge AI is just needed: RISC-V is suitable for battery/cooling-limited scenarios such as smart terminals, Internet of Things equipment, and vehicle cockpits.The only one that can balance computing power and battery lifearchitecture
• data center: AI inference cluster power consumption is reduced by 30%+, significantly reducing TCO (total cost of ownership)

3. Open source and completely get rid of architectural authorization and patent blockade

• Zero licensing fee: Compared to ARM’s annual licensing fees of hundreds of millions + commissions, RISC-Vcompletely free, significantly lowering the threshold of chip design
• Autonomous and controllable: Domestic enterprises/scientific research institutions canFull stack self-research, in-depth modification, permanent commercial use, no risk of technical supply interruption
• Ecological co-construction: China has become the world’s largest contributor to RISC-V (accounting for 50%+ of global shipments) and leads the formulation of multiple standards.

2. Domestic RISC-V AI chips: from catching up to leading (latest progress in 2025-2026)

1. Flagship server CPU (supports large cloud models)

• Alibaba Damo Academy Xuantie C950 (2026.3)
  • 5nm process, 3.2GHz main frequency, single-core SPECint2006 exceeded 70 points (global RISC-V performance record)
  • Built-in tensor acceleration engine (TPE),Native support for Tongyi Qianwen 3, DeepSeek V3 and other large models with hundreds of billions of parameters
  • Memory access bandwidth increased by 4 times, supporting RVA23.1 server standard and CoVE hardware security sandbox
    
• Blue Core Computing Power RISC-V+AI Fusion Server Chip (2026.3)
  • 48 core heterogeneous (32 performance cores + 16 energy efficiency cores), integrating 75 TOPS INT8 computing power
  • The first general-purpose computing + AI intelligent computing native integration, canceling the independent accelerator card, and reducing latency by 50%
  • Already received appointments for testing from banks, operators, and Silicon Valley companies, and will be mass-produced in 2027

2. Edge/terminal AI chips (most widely implemented)

• Vimicro Starlight Smart No. 5 (2025.5)
  • Multi-core heterogeneous GP-XPU architecture, integrated RISC-V CPU+NPU+ISP+VPU
  • A single chip runs DeepSeek 7B/16B, and 8-chip cascade supports 671B full-parameter model
  • Domestic firstFully autonomous and controllableSingle-chip multi-modal large model solution
• EIC7700X/EIC7702
  • High-end edge/server chip, supporting MoE large model sparse inference optimization
  • Deployed Wuhan Cloud Smart City RISC-V server cluster, mixed with x86 scheduling
• Pingtou Ge Xuantie C930
  • Supports RVV 1.0, ResNet-50 inference reduces latency by 62% compared to ARM A76
  • Large-scale use in Alibaba Cloud edge nodes, IoT devices, and industrial control

3. Ecological milestone: NVIDIA CUDA fully supports RISC-V (2025.7)

1. Core meaning (breaking monopoly)

• Global AI Ecological Openness: CUDA supports non-x86/ARM architecture for the first time, RISC-V officially entersMainstream AI computing system
• China's strategic benefits: Domestic RISC-V chips are directly compatible with the CUDA ecosystem.Migration costs approach zero

2. Technical implementation (three major levels)

• Instruction set mapping: CUDA thread/memory model natively adapts to RISC-V RV64G+RVV 1.0, reducing context switching overhead by 40%
• Compiler refactoring: NVCC adds RISC-V backend,CUDA C/C++ compiles directly to RISC-V code
• Full stack compatible: 900+ CUDA acceleration libraries, PyTorch/TensorFlow, and debugging tool chains are fully transplanted
  

3. Value to China’s AI industry

• short term: To ease the pressure of H100/H20 ban, RISC-V server + NVIDIA GPU becomeCompliance and high-performance computing powerNew options
• long term: Domestic chips canSeamless access to the world’s largest AI ecosystem, while maintaining an independent architecture to achieve an open + controllable balance

4. Four major challenges (current bottleneck)

1. There is still a gap in high-performance computing

• Single-thread performance, ultra-large-scale parallelism, and high-bandwidth memory (HBM) synergy are weaker than x86/ARM high-end servers
• Large-scale training (more than 100 billion parameters) does not have enough ecological maturity.Mainly reasoning, supplemented by small-scale training

2. The software ecosystem is imperfect

• The richness of AI frameworks/compilers/debugging tools is lower than that of x86/ARM, and model migration still requires a small amount of adaptation.
• The compatibility of enterprise-level applications and industrial software needs to be improved

3. Risk of instruction set fragmentation

• Manufacturer-defined AI extensions are not uniform, and there are compatibility issues in cross-platform software transplantation
• The industry is advancing RVA23/RVV 1.0, etc.Standardization, gradually converge to fragmentation

4. Insufficient efficiency of multi-core/multi-chip interconnection

• Large-scale cluster synchronization and communication delays are higher than ARM, and supercomputing-level scenarios still need to be optimized.
• Domestic solutions (such as Yisiwei and Xuantie) are quickly catching up through CCIX and self-developed interconnection protocols.

5. China Strategy: Two-wheel drive of policy + market to build an independent AI base

1. Strong policy support

• Big Fund Phase III: Key Investment DirectionsRISC-V CPU/GPU/NPU, EDA, advanced packaging, basic IP
• Government Affairs/State-owned Assets Cloud: Clear procurement prioritiesDomestic RISC-V architecture, the share has reached 67%
• Standards leadership: Leading the RISC-V China Alliance and the RISC-V International Foundation AI Task Force to formulateAutomotive / Industrial / AINational standards

2. Explosion of industrial ecology

• Full chain coverage: Chip (Pingtouge/Yisiwei/Blue Core) → IP (Xinlai/Saifang) → Software (Chinese Academy of Sciences/Huawei) → Machine (Lenovo/Inspur)
• The application is fully implemented：
  • Cloud: Intelligent computing center, cloud computing, large model inference
  • Edge: intelligent cockpit, robots, industrial control, security
  • Terminal: mobile phones, IoT, wearable devices

3. Future Forecast (2026-2028)

• End of 2026: RISC-V inAI edge/terminal market share exceeds 40%, the server inference market exceeded 15%
• 2027: Xuantie C950, blue core computing power, etc.High-End RISC-V ServerLarge-scale commercial use, supporting independent training of hundreds of billions of models
• 2028: RISC-V becomesMainstream architecture of China’s AI chips, with a global share of 24%, completely breaking the x86/ARM duopoly

6. Summary: The optimal path for independent control and the Chinese architecture of the AI industry

• short term: Ease computing power blockade, reduce costs, and quickly build an independent ecosystem
• long term: Leading the next generation of AI chip architecture standards, changing from a follower to a leader